1. Field of the Invention
This invention relates to a data processing circuit, a microcomputer incorporating this data processing circuit, and electronic equipment that is constructed by using this microcomputer.
2. Description of Related Art
In the prior art, a RISC microcomputer that is capable of manipulating 32-bit data uses fixed-length instructions that are 32 bits wide. This is because the use of fixed-length instructions enables a reduction in the time required for decoding the instructions in comparison with the use of variable-length instructions, and it also makes it possible to reduce the size of the circuitry of the microcomputer.
However, even with a 32-bit microcomputer, it isn""t always necessary to use the full 32 bits. Thus, if all of the instructions are written as 32-bit instructions, many of them will contain unused portions so that memory will be used inefficiently.
The present inventors have investigated the idea of a microcomputer that handles fixed-length instructions of a bit width that is narrower than that of the executable data, to improve the usage efficiency without making the control circuitry more complicated.
However, simply cutting 32-bit fixed-length instructions to fit into a fixed 16-bit length, for example, causes problems as described below.
An important feature of a RISC microcomputer is the use of general-purpose registers, whose contents have no pre-assigned meaning. For that reason, when a stack pointer is used, one of the general-purpose register is used as the stack pointer and an instruction that acts upon a general-purpose register is used to implement stack operation.
When coding a process that takes data specified by a memory address obtained by adding a predetermined offset to the stack pointer and transfers it to a predetermined register, using an instruction that acts upon a general-purpose register, for example, it is necessary to include within the object code of that instruction the offset, data specifying the predetermined register, and data specifying the register to be used as the stack pointer.
Thus, if an instruction that acts upon a general-purpose register is used when coding a process that acts upon the stack pointer, a large amount of data has to be specified in the object code, making it difficult to code the details of the instruction within a 16-bit fixed-length. Increasing the instruction length to 32 bits, for example, would result in a large number of instructions that do not particularly need the entire 32 bits, so that many instructions will contain unused portions, leading to a decrease in the efficiency with which memory is used.
In addition, increasing the instruction length will also increase the amount of memory required for storing such instructions, so it is preferable from the point of view of efficient use of memory to not only use fixed-length instructions, but also make the instructions as short as possible.
When a program is executed that was written in a language that secures a storage region for auto-variables linked to the stack pointer, such as programming language C, there are many instructions that act upon the stack pointer, so it is preferable to have efficient coding and execution of instructions that act upon the stack pointer.
In that case, it is therefore preferable to have an architecture that enables the coding and execution of instructions that are as short as possible, when executing a process that acts upon the stack pointer.
It has become common recently to incorporate general-purpose registers internally, particularly with a RISC CPU, to increase capabilities. Providing a large number of registers internally makes it possible for many processes to be executed rapidly within the CPU itself, without having to access memory. If such a large number of internal registers is provided, a large number of registers have to be saved during the process of register save and restoration when an interrupt is processed or a subroutine is called.
The description now turns to a prior-art example of instructions that save and restore the contents of registers, frequently used when entering and leaving a subroutine, even within stack-related instructions.
The instruction set of a microcomputer usually has instructions for saving and restoring the contents of registers in the CPU to and from a stack provided in memory. These are either dedicated instructions or instructions that address registers indirectly.
In the Intel 80386 chip, push, pusha, and pushad instructions are available for writing the contents of registers to the stack, and pop, popa, and popad instructions are available for returning data from the stack to registers.
When the contents of a register are written to the stack by the push instruction, the register has to be specified as an operand, such as xe2x80x98push EAX.xe2x80x99 This example concerns a 32-bit register EAX. If the contents of registers EAX, ECX, EDX, and EBX are all to be written to the stack, this push instruction must be repeated, as follows:
push EAX
push ECX
push EDX
push EBX
If such push and pop instructions are used for each of the registers, the size of the object code increases and a large number of program execution steps is required, leading to delays in the execution time or processing of the program.
That is why the pusha or pushad instruction is used to write the contents of all eight of the general-purpose registers of the 80386 to the stack. pusha operates on the lower 16 bits of each of the eight registers, and pushad operates on the entire 32 bits. The use of pusha and pushad can remove the need to repeat the push instruction eight times.
The pop, popa, and popad instructions act in a similar manner.
Disadvantages of repeating the push instruction include the increased length of program code and the delays in execution caused by executing a fetch for each instruction.
From this point of view, the pusha and pushad instructions provide a large improvement when writing the contents of all eight registers to the stack. However, this is not an advantage when writing fewer than the eight registers, such as four or six registers.
In other words, if the pusha, pushad, popa, and popad instructions of the 80386 operate upon all of the registers, instructions with delayed cycle lengths must be used when there is no need to save and restore the contents of all of the registers. In such a case, one instruction will suffice, but this gives rise to a problem in that the execution cycle of that instruction takes too long.
Similar saving and restoration of the program counter is necessary when program flow branches to a subroutine and returns from the called routine, using instructions such as the call instruction and ret instruction. With a RISC CPU of the prior art, these processes are implemented by software. In other words, the program counter is saved and restored by executing assembler instructions (object code) that declare these processes. This leads to an increase in object code of the call and ret instructions, and the execution of a fetch for each instruction makes the execution speed sluggish.
An objective of this invention is to provide a data processing circuit, microcomputer, and electronic equipment having an architecture that enables efficient coding of processes that act upon the stack pointer within a short instruction length, for execution.
Another objective of this invention is to provide a data processing circuit, microcomputer, and electronic equipment that enables efficient coding of processes that save and restore the contents of registers, with fast processing of interrupts and subroutine calls and returns.
In order to achieve the above objectives, a first aspect of this invention provides a data processing circuit comprising:
a dedicated stack pointer register that is used only for the stack pointer;
decoding means for decoding object code of a group of dedicated stack pointer instructions which have object code specifying the dedicated stack pointer register as an implicit operand and which relate to processing based on the dedicated stack pointer register, and for outputting a control signal based on the object code; and
execution means for executing the group of dedicated stack pointer instructions based on the control signal and the contents of the dedicated stack pointer register.
In this document, xe2x80x9cobject codexe2x80x9d generally refers to program code obtained as a result of translation into machine language by a translation program. With reference to the present invention, it is used in a broad sense to comprise all program coda written in machine language, irrespective of whether this is done by a translation program.
The data processing circuit of this invention is configured that a group of dedicated stack pointer instructions having a dedicated stack pointer register that is used only for the stack pointer and acting upon the dedicated stack pointer register are decoded and executed.
Since this group of dedicated stack pointer instructions has dedicated op code that specifies manipulation of the dedicated stack pointer register, it is not necessary to specify the stack pointer in the operands of the object code. That is to say, this group of dedicated stack pointer instructions uses the dedicated stack pointer register as an implicit operand. This makes it possible to write shorter instructions for manipulating the stack pointer, in comparison with an stack pointer manipulation in which one of the general-purpose registers is allocated to the stack pointer and instructions that act upon that general-purpose register are used.
The present invention therefore makes it possible to provide a data processing circuit that is capable of coding and executing shorter instructions for processes that act upon the stack pointer. It also enables the provision of a data processing circuit that makes efficient use of the memory.
In a second aspect of this invention, the group of dedicated stack pointer instructions comprises a load instruction having data for specifying a transfer register within object code;
the decoding means decodes the load instruction; and
the execution means performs at least one of a transfer of data from a given first area in memory to a given first register and a transfer of data from the given first register to the given first area, based on a memory address specified by the dedicated stack pointer register and a register address specified by the data for specifying a transfer register, when the load instruction is executed.
In this case, the load instruction comprised within the group of dedicated stack pointer instructions is an instruction for transferring data between memory and a register, which means at least one of a transfer from memory to the register and a transfer from the register to memory. Note that this concept also comprises address data, irrespective of the contents of the data. A memory address is an address for specifying an area in memory during data transfer.
Since this load instruction has dedicated op code that specifies an operation relating to the dedicated stack pointer register, it is not necessary to have data specifying the stack pointer in the operands of the object code. It is therefore possible to code within a short instruction length when performing transfers of data between a register and an area in memory having a memory address linked to the stack pointer.
In a third aspect of this invention, the load instruction comprises offset data within the object code that is data relating to an offset for specifying the address of the first area in the memory; and
the execution means determines the memory address according to the contents of the dedicated stack pointer register and the offset data.
In this case, offset data could be an offset that is specified directly as immediate data, or it could be specified indirectly by means such as specifying the address of a register or the like containing the offset. When this load instruction comprising offset data is executed, the memory address necessary for the data transfer is determined on the basis of the contents of the dedicated stack pointer register and the offset data.
This means that instructions can be coded within a short length, for the transfer of data between a register and an area in memory having a memory address that is determined on the basis of the stack pointer and the offset data.
This invention makes it possible to specify any area in the stack, by specifying appropriate offset data, even with a data processing circuit that is configured in such a manner that the stack pointer always indicates a word boundary. Thus the data can be stored in the stack efficiently according to size, enabling an increase in the usage efficiency of the stack.
In a fourth aspect of this invention, the offset data comprises immediate offset data and data size information relating to the size of given data in memory; and
the execution means creates an offset by performing a leftward logical shift on the immediate offset data, based on the immediate offset data and the data size information, and determines the memory address by adding the offset to the contents of the dedicated stack pointer register.
In this case, the immediate offset data is an offset that is specified directly by immediate data. The data size information is the size of data in memory to be transferred.
The data size is usually represented as 2n (where n is greater than 3), such as 8-bit byte data, 16-bit half-word data, or 32-bit word data. Addresses in memory are given in byte units, so that half-word data is placed at half-word boundaries and word data is placed at word boundaries. This means that the least significant bit of the memory address of half-word data is 0 and the least significant two bits of the memory address of word data are 00. Since the address of the stack pointer indicates a word boundary, the least significant bit of the offset is 0 when creating a memory address for half-word data and the least significant two bits of the offset are 00 when creating a memory address for word data.
A leftward logical shift means moving the bit string of the data to the left, and inserting zeros into the bits on the right-hand end of the data that are made vacant by the shift (shift-in bits).
This aspect of the invention makes it possible to code immediate offset data without the lower bits that are determined unambiguously by the data size, because the immediate offset data is shifted to the left in accordance with the data size. This means that the immediate offset data can be specified efficiently, and larger offsets can be specified than in cases in which the data size is specified as is, even if the data size is not bytes.
The use of these instructions makes it possible to select boundary locations that are matched to the size of data when that data is written to memory or read therefrom.
In a fifth aspect of this invention, the group of dedicated stack pointer instructions comprises a stack pointer move instruction for having move data within the object code thereof and for moving the stack pointer;
the decoding means decodes the stack pointer move instruction; and
the execution means modifies the contents of the dedicated stack pointer register based on the move data when the stack pointer move instruction is executed.
Since this stack pointer move instruction has dedicated op code that specifies manipulation of the dedicated stack pointer register, data for specifying the stack pointer in the operands of the object code is not necessary. This makes it possible to code within a short instruction length, when it is desired to move the stack. Thus the amount of instruction coding can be reduced for processes involving data stored in the stack and data that is stored linked to the stack pointer.
Since this aspect of the invention makes it possible to move the stack in a simple manner, it is particularly effective for processes that secure different stack areas for different individual routines. In other words, addresses can be specified over a wide region by moving the stack pointer for each routine, as appropriate.
In a sixth aspect of this invention, the move data comprises immediate data for the stuck pointer move instruction; and
the instruction execution means performs at least one of a process of adding the immediate data for the stuck pointer move instruction and the contents of the dedicated stack pointer register and a process of subtracting the immediate data for the stuck pointer move instruction from the contents of the dedicated stack pointer register.
This aspect of the invention makes it possible to code shorter instruction length for processes that move the stack pointer upward or downward by an amount specified by the immediate data for the stuck pointer move instruction.
In a seventh aspect of this invention, the data processing circuit further comprises:
a plurality of registers provided in a contiguous sequence;
wherein the group of dedicated stack pointer instructions comprises at least one of a sequential push instruction and a sequential pop instruction having data for specifying a plurality of registers in the object code thereof;
the decoding means decodes at least one of the sequential push instruction and the sequential pop instruction; and
the instruction execution means performs at least one of a process of executing a plurality of sequential pushes of data from the plurality of registers to a stack provided in memory and a process of executing a plurality of sequential pops of data from the stack to the plurality of registers, based on the contents of a memory address specified by the dedicated stack pointer register and the data for specifying a plurality of registers, during the execution of at least one of the sequential push instruction and the sequential pop instruction.
A push means the storage of data at the top of a stack provided in memory, and a pop means the fetching of data from this stack. In this case, each of the push processing and pop processing comprises this process of storing or fetching data and the corresponding updating of the stack pointer. An ordinary data processing circuit has a push instruction for storing data or an address from one register to the stack, and a pop instruction for fetching the contents of the stack to a register. Each push and pop instruction transfers data between the register and the stack and updates the stack pointer in correspondence with this transferring.
This means that is it necessary to execute these instructions repeatedly when transferring data between a plurality of registers and the stack.
However, the execution of the sequential push instruction or sequential pop instruction of this aspect of the invention provides the same effect as executing a plurality of push instructions or a plurality of pop instructions in sequence. In other words, it is possible to execute a single instruction to move data between a plurality of registers and the stack, and also update the stack pointer correspondingly. This makes it possible to avoid the increase in size of the object code caused by repeated execution of the push or pop instruction, when transferring data between a plurality of registers and the stack. This also enables an increase in the speed of processing interrupts and subroutine calls and returns, without increasing the number of execution steps in the program and without any wasted cycles.
The data processing circuit of an eighth aspect of this invention further comprises:
n general-purpose registers specified by register numbers 0 to nxe2x88x921;
wherein object code of at least one of the sequential push instruction and the sequential pop instruction comprises a final register number to which one of the register numbers is specified, as the data for specifying a plurality of registers; and
the execution means performs at least one of a process of executing a plurality of sequential pushes of data into a stack provided in memory from a plurality of registers starting from register o to a register specified by the final register number and a process of executing a plurality of sequential pops of data from the stack to a plurality of registers starting from register 0 to a register specified by the final register number, based on the contents of a memory address specified by the dedicated stack pointer register.
When there are plurality of general-purpose registers, there are usually addresses for specifying these registers. This invention specifies these registers by register number, in continuous sequence from 0 to nxe2x88x921.
This aspect of the invention makes it possible to execute at least one of a push or pop of data between memory and a plurality of continuous registers from register 0 to the register with a final register number, by specifying any register number as the final register number. Therefore, the contents of registers can be saved and restored efficiently during the execution of a program having a structure that uses registers in sequence from register number 0.
In a ninth aspect of this invention, the execution means comprises:
write means for writing the contents of a given register that is one of the plurality of registers to a stack provided in memory, based on a memory address specified by the dedicated stack pointer register;
number-of-times-written count means for counting the number-of-times-written of the write means; and
comparison means for comparing the number-of-times-written counted by the count means with the value of the data for specifying a plurality of registers;
wherein the write means comprises:
write memory address generation means for adding a first input and a second input by an adder, and for generating a write memory address for specifying a write destination;
first input control means for providing control such that the first input of the adder is the contents of the dedicated stack pointer register at the start of execution of a sequential dedicated instruction, and is a write address generated subsequently by a write address generation means;
second input control means for outputting an offset used during the writing of one word from the stack to the second input of the adder; and
write means for writing to the stack the contents of a register specified by subtraction processing which uses the data for specifying a plurality of registers and the number-of-times-written, based on the write memory address;
whereby the writing of the contents of the plurality of registers to the stack and the ending of the writing are controlled based on the comparison result of the comparison means.
In a tenth aspect of this invention, the instruction execution means comprises:
read means for reading the contents of a stack provided in memory based on a memory address specified by the dedicated stack pointer register, and storing the contents in a given register of the plurality of registers;
number-of-times-read count means for counting the number-of-times-read of the read means; and
comparison means for comparing the number-of-times-read counted by the count means with the value of the data for specifying a plurality of registers;
wherein the read means comprises:
write memory address generation means for adding a first input and a second input by an adder, and for generating a write memory address for specifying a write destination;
first input control means for providing control such that the first input of the adder is the contents of the dedicated stack pointer register at the start of execution of a sequential dedicated instruction, and is a read address generated subsequently by a read address generation means;
second input control means for outputting an offset used during the writing of one word from the stack to the second input of the adder;
read means for reading the contents of the stack based on the read memory address and storing the contents in a register specified based on the number-of-times-written;
whereby the reading of the contents of the stack and the ending of the reading are controlled based on the comparison result of the comparison means.
This configuration makes it possible to implement the saving to the stack of the contents of a plurality of registers specified by linked sequential values and the restoration of data to a plurality of registers specified by linked sequential values, using only a count means and a simple sequence controller. Since this makes it possible to provide a data processing circuit with a small number of gates, this invention can be applied to one-chip microcomputers or the like.
An eleventh aspect of this invention further comprises:
a program counter register used only for the program counter;
wherein the group of dedicated stack pointer instructions comprises branch instructions that are an instruction for branching to a subroutine and a return instruction from the subroutine;
the decoding means decodes the branch instructions;
the instruction execution means comprises:
means for executing at least one of a process of saving the contents of the program counter register to a given second area of the stack provided in memory and a process of restoring the contents of the second area to the program counter register, based on a memory address specified by the dedicated stack pointer register, during the execution of the branch instruction; and
means for updating the contents of the dedicated stack pointer register based on the saving and restoration.
In this case, a subroutine could be such as an interrupt processing, exception processing, or debugging processing routine. Therefore, an instruction for branching to a subroutine could be such as an instruction that calls a subroutine or the like, or a software interrupt instruction or software debugging interrupt instruction for branching to an interrupt processing, exception processing, or debugging processing routine. Similarly, a return instruction from the subroutine could be a return instruction such as from an interrupt processing, exception processing, and debugging processing routine.
It is usually necessary to save and restore the program counter when branching to a subroutine or returning from a subroutine.
This invention makes it possible to save and restore the program counter simultaneously with the execution of the instruction for branching to the subroutine and the instruction for returning from the subroutine. In other words, the data processing circuit of this aspect of the invention has a circuit structure that enables the saving and restoration of the program counter by either one of instruction, within an instruction for branching to a subroutine and a return instruction from the subroutine. There is therefore no need for instructions for the saving and restoration of the program counter, which is necessary when branching to a subroutine and returning therefrom, enabling a reduction in the number of instructions. This makes it possible to increase the speed of processing during a branch to another routine, such as subroutine call and return, without wasting cycles.
When a software interrupt instruction is generated, for example, it is necessary to save and restore the processor status register that holds the current state of the CPU or other data processing circuit. It is therefore preferable to perform this saving and restoration of the processor status register simultaneously with the execution of an instruction such as a software interrupt instruction.
A twelfth aspect of this invention relates to a data processing circuit comprising a plurality of registers provided in a contiguous sequence and a stack pointer allocated to one of a plurality of general-purpose registers, the data processing circuit further comprise;
means for decoding object code of an instruction that is at least one of a sequential push instruction and sequential pop instruction that each have data for specifying a plurality of registers within object code and for outputting a control signal on the basis of the object code; and
means for performing at least one of a process of executing a plurality of sequential pushes of data from the plurality of registers to a stack provided in memory and a process of executing a plurality of sequential pops of data from the stack to the plurality of registers, based on the control signal, the contents of a memory address specified by the dedicated stack pointer register, and the data for specifying a plurality of registers, during the execution of at least one of the sequential push instruction and the sequential pop instruction.
This aspect of the invention relates to a sequential push instruction and a sequential pop instruction that are used when a general-purpose register is used as the stack pointer.
The execution of this sequential push instruction or sequential pop instruction has the same effect as the execution of a plurality of push instructions in sequence or the execution of a plurality of pop instructions in sequence. In other words, the movement of data between a plurality of registers and the stack and the corresponding updating of the stack pointer are enabled by the execution of single instructions. This makes it possible to avoid the increase in object code size caused by repeated executions of push or pop instructions, when transferring data between a plurality of registers and the stack. This also enables an increase in the speed of processing interrupts and subroutine calls and returns, without increasing the number of execution steps in the program and without any wasted cycles
In a thirteenth aspect of this invention, this data processing circuit uses instructions of a RISC.
A RISC data processing circuit is designed with the objectives of reducing the dimensions of the hardware and increasing the speed thereof. Thus, a RISC data circuit has many general-purpose registers. Reduction of the number of instructions is achieved by using only an instruction set which has universality.
Therefore, with a RISC data processing circuit, the stack pointer is allocated to a general-purpose register, and the processing uses an instruction set that acts upon this general-purpose register when manipulating the stack pointer. However, this method leads to an increased instruction length, so that memory is used inefficiently.
This aspect of the invention makes it possible to increase the efficiency with which memory is used by a RISC data processing circuit, by reducing the instruction length.
In the data processing circuit of a fourteenth aspect of this invention, a fixed-length instruction is decoded and execution is based on that instruction.
When the use of fixed-length instructions is compared with the use of variable-length instructions, it is possible to shorten time required for decoding the instructions and reduce the dimensions of the data processing circuit itself. To ensure that memory is used efficiently when fixed-length instructions are employed, by avoiding the creation of unused portions within instruction, it is preferable to have little variation in the number of bits necessary for each instruction, so that they are as short as possible.
This aspect of the invention makes it possible to reduce the length of instructions that act upon the stack pointer and thus tend to become too long. It is therefore possible to avoid the creation of unused portions within instructions, even when fixed-length instructions are employed, so that memory can be used more efficiently.
The microcomputer of a fifteenth aspect of this invention comprises the previously described data processing circuit of this invention, storage means, and input and output means for inputting data from and for outputting data to external devices.
This aspect of the invention makes it possible to provide a microcomputer with a fast processing speed and efficient usage of memory.
In the microcomputer of a sixteenth aspect of this invention, a program that is executed thereby uses a program language that secures a storage region for auto-variables by using the stack pointer.
An example of a language that secures a storage region for auto-variables by using the stack pointer is C language. When the microcomputer of this invention executes a program written in such a language, the processing speed and memory usage efficiency can be increased effectively.
Electronic equipment in accordance with a seventeenth aspect of this invention comprises one of the above described microcomputers of this invention.
This aspect of the invention makes it possible to provide inexpensive, but sophisticated, electronic equipment that is facilitated by a data processing circuit that has a fast processing speed and a highly efficient usage of memory.